FED technology has recently come into favor as a technology for developing low power, flat panel displays. This technology uses an array of cold cathode emitters and cathodoluminescent phosphors for conversion of energy from an electron beam into visible light. Part of the desire to use FED technology for flat-panel displays is that such technology is conducive to producing flat screen displays having high performance, low power and light weight.
Referring to FIG. 1, a representative cross-section of a prior art FED 100 is shown generally. As is well known, FED technology operates on the principal of cathodoluminescent phosphors being exited by cold cathode field emission electrons. The general structure of FED 100 includes semiconductor layer, or baseplate, 102 and a relatively thin conductive layer formed over the baseplate 102. Baseplate 102, and/or the thin conductive layer formed over baseplate 102 and the other structures to be discussed below may be considered as part of a substrate, where the term substrate, as used herein, refers to one or more semiconductor layers or structures that may include active or operable portions of semiconductor devices.
The thin conductive structure may be formed from doped polycrystalline silicon or metal that is deposited on baseplate 102 in a conventional manner. This thin conductive structure serves as the emitter electrode. The thin conductive structure is usually deposited on baseplate 102 in strips that are electrically connected. In FIG. 1, a cross-section of strips 104, 106, and 108 is shown. The number of strips for a particular device will depend on the size and desired operation of the FED.
At predetermined sites on the respective emitter electrode strips, spaced apart patterns of micropoints are formed. In FIG. 1, micropoint 110 is shown on strip 104, micropoints 112, 114, 116, and 118 are shown on strip 106, and micropoint 120 is shown on strip 108. With regard to the patterns of micropoints on strip 106, a square pattern of 16 micropoints, which includes micropoints 112, 114, 116, and 118, may be positioned at that location. However, it is understood that one or a pattern of more than one micropoint may be located at any one site. For purposes of discussion, the combination of one or more micropoints disposed over a conductive layer or region which, in turn, resides over or in a substrate is referred to as a micropoint assembly. For example, FIG. 1 identifies micropoint assembly 119.
Preferably, each micropoint resembles a cone. The forming and sharpening of each micropoint is carried out in a known manner such as disclosed in U.S. Pat. Nos. 3,970,887 and 5,372,973, both of which are hereby incorporated by reference in their entirety for all purposes. The micropoints may be constructed of a number of materials, such as single crystal silicon. Moreover, to ensure the optimal performance of the micropoints, the tips of the micropoints can be coated or treated with a low work function material.
After forming the micropoints, dielectric insulating layer 122 is deposited over emitter electrode strips 104, 106, and 108, and the patterned micropoints located at predetermined sites on the strips. The insulating layer may be made from silicon dioxide (SiO.sub.2).
A conductive layer is disposed over insulation layer 122. This conductive layer forms extraction structure 132. The extraction structure 132 is a low potential anode that is used to extract electrons from the micropoints. Extraction structure 132 may be made from a variety of materials including chromium, molybdenum, doped polysilicon or silicided polysilicon. Extraction structure 132 may be formed as a continuous layer or as parallel strips. If parallel strips form extraction structure 132, it is referred to as an extraction grid, and the strips are disposed perpendicular to emitter electrode strips 104, 106 and 108 thereby forming the rows of the matrix structure. Whether a continuous layer or strips are used, once either is positioned on the insulating layer, they are appropriately etched by conventional methods to surround but be spaced away from the micropoints.
At each intersection of the extraction and emitter electrode strips or at desired locations along emitter electrode steps when a continuous extraction structure is used, a micropoint or pattern of micropoints are disposed on the emitter strip. Each micropoint or pattern of micropoints are meant to illuminate one pixel of the screen display.
Once the lower portion of the FED is formed according to either of the methods described above, faceplate 140 is fixed a predetermined distance above the top surface of the extraction structure 132. Typically, this distance is several hundred micrometers. This distance may be maintained by spacers or other conventional methods. Representative spacers 136 and 138 are shown in FIG. 1.
Faceplate 140 is a cathodoluminescent screen that is constructed from clear glass or other suitable material. A conductive material, such as indium tin oxide ("ITO") is disposed on the surface of the glass facing the extraction structure. ITO layer 142 serves as the anode of the FED. A high vacuum is maintained in area 134 between faceplate 140 and baseplate 102.
Black matrix 149 is disposed on this surface of the ITO layer 142 facing extraction structure 132. Black matrix 149 defines the discreet pixel areas for the screen display of the FED. Phosphor material is disposed on ITO layer 142 in the appropriate areas defined by black matrix 149. Representative phosphor material areas that define pixels are shown at 144,146 and 148. These pixels are aligned with the openings in extraction structure 132 so that a micropoint or group of micropoints that are meant to excite phosphor material are aligned with that pixel. Zinc oxide is an example of a suitable material for the phosphor material since it can be excited by low energy electrons.
A FED has one or more voltage sources that maintain emitter electrode strips 104, 106 and 108, extraction structure 132, and ITO layer 142 at three different potentials for proper operation of the FED. Emitter electrode strips 104, 106 and 108 are at "-" potential, extraction structure is at a "+" potential, and the ITO layer 142 at a "++" potential. When such an electrical relationship is used, extraction structure 132 will pull an electron emission stream from micropoints 110, 112, 114, 116, 118 and 120. Thereafter, ITO layer 142 will attract the freed electrons.
The electron emission streams that emanate from the tips of the micropoints fan out conically from their respective tips. The majority of the electrons strike the phosphors at 90.degree. to the faceplate while the remainder strike it at various acute angles. The contrast and brightness of the screen display of the FED are optimized when the emitted electrons strike or impinge upon the phosphors at 90.degree..
In devices such as FED 100, it is difficult to control current through the micropoints (e.g., 110-120). Nonuniform current can create brightness non-uniformity in the display and excessive currents can cause failure in the FED. When a FED is first turned on, local degasification occurs which can produce electric arcs between components, such as micropoint 118 and extraction structure 132. Additionally, because the components in the FED are small, manufacturing defects can cause a micropoint to be electrically shorted to structure 132. These problems can cause enough current to be drawn through one of the micropoints to destroy it and other surrounding micropoints, thus resulting in damage or even destruction of the FED.
U.S. Pat. No. 4,940,916 discloses a FED having a continuous resistive layer disposed along the length of each of a number of conductive strips in the cathode. This layer limits current flowing through each conductive strip. With this approach, current for many individual micropoints passes through the same underlying resistive layer. This layer significantly impacts the layout and/or physical dimensions of other FED elements since it is continuously disposed between a conductive layer and corresponding micropoints. Specifically, its inclusion requires modification and/or displacement of the underlying conductive layer and/or an overlying dielectric insulating layer. Further, using a continuous resistive layer rather than an individual resistor dedicated to each micropoint, may result in unequal amounts of current flowing from adjacent micropoints to the same pixel rather than having all micropoints dedicated to the same pixel each provide an equal amount of current to the pixel.
In contrast, U.S. Pat. No. 3,789,471 discloses a micropoint electron source in which each micropoint rests atop a pedestal made from an electrically resistive material. However, each pedestal (disposed directly on top of a planar conductive layer) requires a separate and different deposition step from the micropoint and therefore complicates FED fabrication. Specifically, the pedestal is formed by deposition of emitter material that is passed through a mask having a uniform dedicated aperture. Conversely, the associated micropoint is formed by deposition of emitter material through a modified dedicated mask such that the aperture gradually reduces in size during deposition
In addition to complicating FED fabrication, micropointdedicated apertures introduce micropoint-specific variables into this process (e.g., aperture size). Accordingly, the dimensions of the resulting structure (e.g., height) will vary independently from point-to-point dependent upon, for example, aperture size. Such variation will create equally independent fluctuations in resistivity. As a result, control of resistive value must be maintained at the individual micropoint level to compensate for any lack of uniformity introduced by micropoint-specific variables.
U.S. Pat. No. 3,812,559 discloses pyramid-like micropoints that may be made from resistive, insulating or composite materials. These structures are fabricated using the same process as described above in U.S. Pat. No. 3,789,471 and, therefore, are subject to the same limitations.
Accordingly, it is desirable to provide an improved micropoint architecture that includes resistive structures created through conventional processing techniques and applied uniformly to select, multiple FED elements (such as micropoints and conductors) with minimum impact to remaining FED elements.